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Computer Science Organization | Internal Communication of Processor

In this article, we are going to learn about the internal communication of processor and discuss about the communication of processor with memory devices and input output devices.
Submitted by Prerana Jain, on July 08, 2018

Internal communication

CPU of the computer system communicates with the memory and the I/O devices in order to transfer data between them. However the method of communication of the CPU with memory and I/O devices in different. The CPU may communicate with the memory either directly or through the Cache memory. However, the communication between the CPU and I/O devices is usually implemented with the help of interface. Therefore the internal communication of a processor in the computer can be divided into two major categories:

1. Processor to memory communication
2. Processor to I/O devices communication

1) Processor to memory communication

The direct communication between the processor and memory of the computer system is implemented with the help of two registers. Memory Address register (MAR) and Memory Buffer register (MBR). The processor can interact with the memory of the computer system for reading data from the memory as well as for writing data on to the memory. The MAR and MBR register play a very important role in implementing this type of communication. These registers are the special purpose register of the processor.

The processor perform the following steps to read the data:

1. First, the processor loads the address of the memory location from where data is in the reader into the MAR register using the address bus.
2. After loading the address of the memory location the processor issues the READ control signal through the control bus. The control bus is used to carry the commands issued by the processor and status signals are generated by the various devices in response to these commands.
3. After receiving the READ control signal the memory loads the data into the MDR register from the location specified in the MAR register using the Data bus.
4. Finally, the data is transferred to the processor.

The processor perform the following steps for writing the data:

1. First, the processor loads the address of the memory location where data is to be written in the MAR register using the address.
2. After loading the address of the memory location the processor loads the desired data in the MDR register using the Data bus.
3. After this, the processor issues the WRITE control signal to the memory using the control bus.
4. Finally, the memory stores the data loaded in the MDR register at the desired memory location.

2) Processor to I/O devices communication

The communication between the I/O devices and the processor of the computer system is implemented using an interface unit. In a computer system data is transferred from an input device to the processor and from the processor to an output device.

Some steps are performed while transferring data from I/O devices:

1. The data is to be transferred is placed on the data bus by the input devices which transfer single bytes of data at a time.
2. The input devices then issue the data valid signal through the devices control bus to the data register, including that the data is available on the data bus.
3. As the data register now holds the data the For the flog bit of the same register in the interface unit.
4. The processor the now issue an I/O read signal to the data registers in the interface unit.
5. The data register then places the data on the data on the data bus connected to the processor of the computer system.

Some steps are performed while transferring data to output devices:

1. The processor laces the data that needs to be transferred on the data bus connected to the data register of the interface unit.
2. The CPU also places the address of the output devices on the devices address bus.
3. After placing the address and data on the appropriate buses, CPU issue the I/O write signal, which writes the data on the data register.
4. The data register of the interface unit issue a data accepted signal through the control bus to the processor.
5. The interface unit then places the data stored in the data register on to the data bus connected to the device controller of the output devices.
6. The output devices then receive the data and send to acknowledgment signal to the processor.