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What is Advanced Programmable Interrupt Controller (APIC)?

Advanced Programmable Interrupt Controller (APIC): Here, we are going to learn about the Advanced Programmable Interrupt Controller, its history, Integrated Local APICS, I/O APICS, etc.
Submitted by Anushree Goswami, on January 08, 2021

APIC: Advanced Programmable Interrupt Controller

APIC is an abbreviation of "Intel's Advanced Programmable Interrupt Controller". It is a familiar associated group of interrupt controllers. In comparison to the 8259 Programmable Interrupt Controller (PIC), the APIC is more highly developed, which specifically allowing the production of multiprocessor systems. It is one of the numerous architectural designs planned to resolve interrupt routing effectiveness concerns in multiprocessor computer systems.

  • The APIC is a distributed architecture design, with a local component (LAPIC) generally included in the processor itself, and an elective I/O APIC on a system bus.
  • The primary APIC was the 82489DX – it was a discrete chip that worked both as local and I/O APIC. The 82489DX allowed the manufacturing of symmetric multiprocessor (SMP) systems with the Intel 486 and initial Pentium processors.

Discrete APIC

  • The first-generation Intel APIC chip, the 82489DX, which was intended to be used with Intel 80486 and initial Pentium processors, is in point of fact a peripheral local and I/O APIC in one circuit. The Intel MP 1.4 specification alludes to it as "discrete APIC" in comparison with the "integrated APIC" established in the majority of the Pentium processors. The 82489DX had 16 interrupt lines; it also had an eccentricity that it could drop a number of ISA interrupts.
  • In a multiprocessor 486 system, each CPU had to be coupled with its own 82489DX; furthermore, an additional 82489DX had to be used as I/O APIC. The 82489DX could not imitate the 8259A (XT-PIC) therefore these also had to be integrated as physical chips for compatibility towards the back. The 82489DX was wrapped up as a 132-pin PQFP.

Integrated Local APICS

  • Local APICs (LAPICs) supervise the entire peripheral interrupts for a number of the particular processor in an SMP system.
  • Furthermore, they are able to acknowledge and produce inter-processor interrupts (IPIs) between LAPICs. LAPICs may hold up to 224 functional interrupt vectors from an I/O APIC.
  • Vector numbers 0 to 31, out of 0 to 255, are set aside for exception handling by x86 processors.

I/O APICS

  • I/O APICs consist of a redirection table, which is used to route the interrupts it accepts from external buses to one or more local APICs.
  • The first-generation keen and committed I/O APIC, the 82093AA, had backup and maintenance for 24 interrupt lines. It was wrapped up as a 64-Pin PQFP. The 82093AA is generally associated with the PIIX3 and used its integrated legacy 8259 PICs.

Reference: Advanced Programmable Interrupt Controller


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