What is the full form of BSB?

Full form of BSB: Here, we are going to learn what does BSB stands for? BSB – which is an abbreviation of "Back-Side Bus" in Computer Acronyms/Abbreviations, etc.
Submitted by Anushree Goswami, on May 18, 2020

BSB: Back-Side Bus

BSB is an abbreviation of the "Back-Side Bus".

It was an internal computer bus that links the central processing unit to the cache memory of Level 2. In personal computer microprocessor architecture, there are two categories of buses that transmit data towards the computer’s CPU and from a computer's CPU.

These buses are:

  1. The frontside bus: the frontside bus transmits data between the CPU and memory controller hub.
  2. The backside bus: the backside bus transfers data between the CPU and the computer's secondary cache or level 2 cache.

The CPU stores data in the cache memory that is frequently used and requires to be quickly recovered. This enables the CPU of a computer to operate and function more proficiently and powerfully as it can reiterate processes more rapidly.

The enhancement in CPU transmission with cache memory was done by backside bus by turning down wide-ranging signals and getting rid of more than enough actions and measures. At the time when the latest processors corresponding to the second-generation Pentium III started to include as a feature on Level 2 cache, the Back-side bus architecture was suspended. At present, the majority of personal computers put together Level 2 and Level 3 cache memory into the CPU, which makes the backside bus outdated. There was no cache memory of Level 2 or Level 3 in the former personal computers. The backside bus was used to access cache memory from the outside as an alternative, which was at that time not much rapid, however in contrast to using RAM through the frontside bus; it is still to a great extent far more rapid.

A microprocessor architecture that uses both frontside and backside bus is known as dual-bus architecture or dual independent bus (DIB) architecture. In the architecture of dual-bus, a system using one bus as a frontside that links to the main memory and use an additional bus as a backside that links to the cache memory of Level 2.

Reference: Back-side_bus

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