What is the full form of DDR4 SDRAM?

Full form of DDR4 SDRAM: Here, we are going to learn what does DDR4 SDRAM stands for? DDR4 SDRAM – which is an abbreviation of "Double Data Rate 4 Synchronous Dynamic Random-Access Memory" in Computer Acronyms/Abbreviations, etc.
Submitted by Anushree Goswami, on November 23, 2020

DDR4 SDRAM: Double Data Rate 4 Synchronous Dynamic Random-Access Memory

DDR4 SDRAM is stands for "Double Data Rate 4 Synchronous Dynamic Random-Access Memory". It consists of a high bandwidth interface.

DDR4 SDRAM History

  • In 2014, DDR4 SDRAM was launched publically in the market.
  • In 2014, Intel's Haswell roadmap made publically known the first use of DDR4 SDRAM by the company in Haswell-EP processors.

Basis of Features

Features contained by DDR4 SDRAM have the basis of:

  • Power savings
  • Performance enhancement
  • Manufacturability
  • Reliability improvements


  • DDR4 chips make use of a 1.2 V supply in the company of a 2.5 V auxiliary supply in case of wordline boost known as VPP.
  • It uses memory, which is provided in 288-pin dual in-line memory modules (DIMMs).
  • DDR4 SO-DIMMs uses 260 pins, whose length measurement is 0.5 mm; width is 2.0 mm and height is 30 mm, which stay similar to the DDR3 SO-DIMMs.

DDR4 SDRAM Advantages

  • It consists of a higher module density.
  • It consists of lower voltage supplies.
  • It consists of higher data rate transfer speeds.
  • Its standard enables in case of DIMMs of up to 64 GiB in memory size.
  • It consists of higher speed operation devoid of irrational power and cooling necessities due to lower voltage supplies.
  • Its features enhance and develop performance, manufacturability, power, reliability, and stacking facilities in support of the enterprise, ultrathin, automotive, cloud, tablet, and embedded markets.

DDR4 module of JEDEC standard

  • CAS latency (CL): It is the Clock cycles connecting the process of transferring a column address to the space of memory and the opening of data in the act of response.
  • tRCD: It is the Clock cycles connecting row activate and reads/writes.
  • tRP: It is the Clock cycles connecting row pre-charge and activate.

Reference: DDR4 SDRAM

Algo tagged in: Dictionary – 'C'



Comments and Discussions



Languages: » C » C++ » C++ STL » Java » Data Structure » C#.Net » Android » Kotlin » SQL
Web Technologies: » PHP » Python » JavaScript » CSS » Ajax » Node.js » Web programming/HTML
Solved programs: » C » C++ » DS » Java » C#
Aptitude que. & ans.: » C » C++ » Java » DBMS
Interview que. & ans.: » C » Embedded C » Java » SEO » HR
CS Subjects: » CS Basics » O.S. » Networks » DBMS » Embedded Systems » Cloud Computing
» Machine learning » CS Organizations » Linux » DOS
More: » Articles » Puzzles » News/Updates

© some rights reserved.