Master-Slave JK Flip Flop

In this article, we are going to discuss in detail about the concepts of Master-Slave JK Flip Flop, how it is designed and implemented? How it solves the problem of race-around condition that occurred in the case of JK flip-flop?
Submitted by Saurabh Gupta, on February 07, 2021

The problem in JK-Flip Flop: As we have already discussed in our previous article Race Around Condition and T-Flip Flop, there exists a problem of toggling in the usual JK flip flops. To overcome this issue, we have already discussed the concept of Edge triggered JK flip-flop in the article Introduction to JK-Flip Flop. Now, we will see how we can use Master-Slave JK-flip flops to overcome the problem of toggling?

Master-Slave JK-Flip Flop

When edge-triggered flip flops were not invented in the past, then Master-Slave JK-flip flop were used to remove the problem of the race around condition in JK flip flop.

Construction: A master-slave JK flip flop is constructed using two components: master and the slave. The master component consists of clocked JK-flip flop and the slave part is made up of clocked SR-flip flop. The output of the master component is fed as an input to the slave component. The clock signal is connected directly to the master flip-flop but is converted via an inverter to the slave flip-flop. The logic circuit and logic diagram of master-slave JK flip flop is shown below:

Master-Slave JK Flip Flop (1)

Master-Slave JK Flip Flop (2)

Working of Master-Slave JK Flip Flop

When the positive clock pulse is provided via the clock, the information present at the J and K input is transmitted to the output of the master flip flop and it is held there until the negative clock pulse occurs, after which it is allowed to pass through to the input of slave flip flop. Then, the output of the slave flip-flop is connected back as the third input of the master JK flip flop.

We can derive a truth table using the circuit provided above:

Master-Slave JK Flip Flop (3)

When J=1 and K=1, master flip flop toggles on '+ve' clock and slave then copies the output of master. When the '-ve' clock cycle at this instant arrives, feedback inputs to the master flip-flop are complemented but as it is '-ve' half of the clock pulse master flip flop remains inactive. This prevents the race around the condition.

Input and Output waveform of master-slave JK flip flop is drawn as:

Master-Slave JK Flip Flop (4)



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